Hot-carrier reliability evaluation for CMOS devices and circuits

As CMOS scaling continues, the traditional DC device-level hot-carrier reliability criteria becomes difficult to meet for newer generations of technology. In order to satisfy hot-carrier reliability requirements by using AC circuit-level criteria, issues of AC device degradation under circuit operation and impact of device degradation on circuit performance need to be examined. In order to satisfy the wide range of bias conditions in AC circuit environments, NMOSFET hot-carrier degradation models are investigated in detail. Accurate calibration of these models to a particular technology is shown to require accounting for the asymptotic and variable power-law time dependence of hot-carrier degradation associated with the LDD structure, and the impact of the local oxide electric field on the critical energy for interface damage. In addition, statistical analysis is used to determine the prediction intervals within which hot-carrier lifetime can be estimated, and to offer insight into developing more efficient and precise testing methodologies. Evaluation of hot-carrier degradation for basic digital and analog subcircuits is conducted with experimental verification using circuit test structures. The AC device degradation mechanisms due to hot carriers are studied under high-frequency digital circuit operation. Two new degradation phenomena are observed at these high frequencies. First, voltage overshoot, due to internal MOSFET parasitic capacitances, causes enhanced hot-carrier degradation. Second, the quasi-static approximation is found to be invalid at high frequencies. For NMOSFETs, fast voltage transitions are found to induce different degradation dynamics; for PMOSFETs, donor-type interface-state generation and electron detrapping both become significant. The impact of NMOSFET hot-carrier-induced degradation on CMOS analog subcircuit performance is evaluated. Because of circuit design requirements, most NMOSFETs used for analog applications are biased in the saturation region with a low gate-to-source voltage. Under such operating conditions, hole trapping is the dominant 2 mechanism to affect analog NMOSFET device performance. The hot-carrier-induced degradation of analog subcircuit performance is also found to be quite sensitive to the particular circuit design and operating conditions. Circuit performance and reliability tradeoffs are examined. Thesis Supervisor: Dr. James E. Chung Title: Assistant Professor of Electrical Engineering